This application relates to a reset architecture for an opamp. Various applications such as set top boxes, video applications, and, powerline communications demand for high-speed, low power analog to digital converters (ADCs). As discussed in [1] T. N. Anderson et al, “A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.181m Digital CMOS”, IEEE Journal of Solid-State Circuits, pp. 1506-1513, July 2005; and [2] S. Lewis and P. Gray, “A pipelined 5 MHz 9b ADC”, ISSCC Digest of Technical Papers, pp. 210-211, February 1987, pipelined ADC's can provide a high speed ADC solution. Typically, the stages used in a pipelined ADC include, among other things, a multiplying digital to analog converter (MDAC) that receives an input voltage as well as output from a pair of comparators. The MDAC includes an opamp that is used by the MDAC to multiply the MDAC input voltage by a fixed number and also add or substract a voltage to the input voltage based on the signals received from the comparators.
There is a need for an improved reset architecture for opamps, including for example, opamps used in pipelined analog to digital converters.